Many microprocessors and subsystems use a global synchronizing clock to sequence through their operations. Global circuit synchronization streamlines the design and interfacing of the digital logic structures while reducing the pipeline sequencing overhead. But the worst-case design constraints, based on environment, process, and a single critical logic path, limit a synchronous system's ability to fully use the available semiconductor performance. Synchronous operation and communication also restrict efficient data transfer between devices having differing processing rates or access procedures. Synchronous systems are widely used throughout the digital system industry. Nevertheless, it is preferable to use more of the available semiconductor performance while providing efficient processing-rate independent interfaces.
Asynchronous systems provide an alternative to synchronous systems by reducing synchronous operating constraints. Nevertheless, typical asynchronous systems have shortcomings. Such shortcomings include complex logic structures and sequencing overheads resulting from completion detection and handshaking circuits.
Thus, a need has arisen for a method and system for self-timed processing, in which more of the available semiconductor performance is used relative to previous synchronous systems while providing efficient processing-rate independent interfaces. Also, a need has arisen for a method and system for self-timed processing, in which adaptive operation, efficient and flexible interfaces, low power consumption, and a wide environmental operating range are provided. Further, a need has arisen for a method and system for self-timed processing, in which complex logic structures and sequencing overheads are decreased relative to previous asynchronous systems.